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d a t a sh eet product speci?cation supersedes data of may 1995 file under integrated circuits, ic22 1996 aug 20 integrated circuits saa7165 video enhancement and digital-to-analog processor (veda2)
1996 aug 20 2 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 features cmos circuit to enhance video data and to convert luminance and colour-difference signals from digital-to-analog digital colour transient improvement block (dcti) to increase the sharpness of colour transitions. the improved pin-compatible saa7165 can supersede the saa9065 16-bit parallel input for 4 : 1 : 1 and 4:2:2 yuv data data clock input llc (line-locked clock) for a data rate up to 36 mhz 8-bit luminance and 8-bit multiplexed colour-difference formats (7-bit formats optional) mc input to support various clock and pixel rates formatting yuv input data; 4 :2:2 format, 4:1:1 format and filter characteristics selectable href input to determine the active line (number of pixels) controllable peaking of luminance signal coring stage with controllable threshold to eliminate noise in luminance signal interpolation filter suitable for both formats to increase the data rate in chrominance path polarity of colour-difference signals selectable all functions controlled via i 2 c-bus separate digital-to-analog converters (9-bit resolution for y; 8-bit for colour-difference signals) 1 v (p-p)/75 w outputs realized by two resistors no external adjustments. quick reference data ordering information symbol parameter min. typ. max. unit v ddd digital supply voltage 4.5 5 5.5 v v dda analog supply voltage 4.75 5 5.25 v i dd(tot) total supply current - tbf - ma v il low-level input voltage on yuv-bus - 0.5 - +0.8 v v ih high-level input voltage on yuv-bus 2 - v ddd + 0.5 v f llc input data rate -- 36 mhz v o(p-p) output signals y, (r - y) and (b - y) (peak-to-peak value) - 2 - v r l output load resistance 125 -- w ile dc integral linearity error in output signal (8-bit data) -- 1 lsb dle dc differential error in output signal (8-bit data) -- 0.5 lsb t amb operating ambient temperature range 0 - 70 c type number package name description version saa7165wp plcc44 plastic leaded chip carrier; 44 leads sot187-2
1996 aug 20 3 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 block diagram handbook, full pagewidth meh464 interpolation filter y formatter dcti saa7165 y u v data switch dac 3 41 42 cur v dda4 25 w 36 peaking and coring dac 2 dac 1 uv formatter timing control i 2 c-bus control test control 40 v dda3 37 v dda2 32 v dda1 31 v ddd2 12 13 v ssd1 v ddd1 data clock 21 to 14 8 y7 to y0 11 to 4 24 27 25 26 28 29 8 uv7 to uv0 mc llc href reset scl sda yuv-bus i 2 c-bus 25 w 33 (r - y) (b - y) 25 w 39 1 y c uv refl uv refl y 2 c y 43 44 30 v ssd2 22 ap 23 sp 34 v ssa1 35 v ssa2 38 v ssa3 3 sub fig.1 block diagram.
1996 aug 20 4 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 pinning symbol pin description refl y 1 low reference of luminance dac (connected to v ssa1 ) c y 2 capacitor for luminance dac (high reference) sub 3 substrate (connected to v ssa1 ) uv0 4 uv signal input bit uv7 (digital colour-difference signal) uv1 5 uv signal input bit uv6 (digital colour-difference signal) uv2 6 uv signal input bit uv5 (digital colour-difference signal) uv3 7 uv signal input bit uv4 (digital colour-difference signal) uv4 8 uv signal input bit uv3 (digital colour-difference signal) uv5 9 uv signal input bit uv2 (digital colour-difference signal) uv6 10 uv signal input bit uv1 (digital colour-difference signal) uv7 11 uv signal input bit uv0 (digital colour-difference signal) v ddd1 12 +5 v digital supply voltage 1 v ssd1 13 digital ground 1 (0 v) y0 14 y signal input bit y7 (digital luminance signal) y1 15 y signal input bit y6 (digital luminance signal) y2 16 y signal input bit y5 (digital luminance signal) y3 17 y signal input bit y4 (digital luminance signal) y4 18 y signal input bit y3 (digital luminance signal) y5 19 y signal input bit y2 (digital luminance signal) y6 20 y signal input bit y1 (digital luminance signal) y7 21 y signal input bit y0 (digital luminance signal) ap 22 connected to ground (action pin for testing) sp 23 connected to ground (shift pin for testing) mc 24 data clock cref (e.g. 13.5 mhz); at mc = high, the llc divider-by-two is inactive llc 25 line-locked clock signal (ll27 = 27 mhz) href 26 data clock for yuv data inputs (for active line 768y or 640y long) reset 27 reset input (active low) scl 28 i 2 c-bus clock line sda 29 i 2 c-bus data line v ssd2 30 digital ground 2 (0 v) v ddd2 31 +5 v digital supply voltage 2 v dda1 32 +5 v analog supply voltage for buffer of dac 1 (r - y) 33 (r - y) output signal (analog signal) v ssa1 34 analog ground 1 (0 v) v ssa2 35 analog ground 2 (0 v) (b - y) 36 (b - y) output signal (analog colour-difference signal) v dda2 37 +5 v analog supply voltage for buffer of dac 2 v ssa3 38 analog ground 3 (0 v) y 39 y output signal (analog luminance signal) v dda3 40 +5 v analog supply voltage for buffer of dac 3
1996 aug 20 5 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 cur 41 current input for analog output buffers v dda4 42 supply and reference voltage for the three dacs c uv 43 capacitor for chrominance dacs (high reference) refl uv 44 low reference of chrominance dacs (connected to v ssa1 ) symbol pin description fig.2 pin configuration. handbook, full pagewidth saa7165 meh465 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 y sda v ssa3 v ssd2 v ssa2 v ssa1 v dda2 v dda1 v ddd2 (b - y) (r - y) uv1 uv0 sub c y refl y refl uv c uv cur v dda4 v dda3 uv2 uv3 uv4 uv5 uv6 uv7 y0 y1 y2 y3 y4 y5 y6 y7 ap sp mc llc href reset scl v ddd1 v ssd1
1996 aug 20 6 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 functional description the cmos circuit saa7165 processes digital yuv-bus data up to a data rate of 36 mhz. the data inputs y7 to y0 and uv7 to uv0 (see fig.1) are provided with 8-bit data. the data of digital colour-difference signals u and v are in a multiplexed state (serial in 4 : 2:2or4:1:1 format; tables 2 and 3). data is read with the rising edge of llc (line-locked clock) to achieve a data rate of llc at mc = high only. if mc is supplied with the frequency cref ( 1 2 llc for example), data is read only at every second rising edge (see fig.3). the 7-bit yuv input data are also supported by means of bit r78 (r78 = 0). additionally, the luminance data format is converted for internal use into a twos complement format by inverting the msb. the y input byte (bits y7 to y0) represents luminance information; the uv input byte (bits uv7 to uv0) represents one of the two digital colour-difference signals in 4 :2:2 format (table 2). the href input signal (href = high) determines the start and the end of an active line (see fig.3) and the number of pixels respectively. the analog output y is blanked at href = low, the (b - y) and (r - y) outputs are in a colourless state. the blanking level can be set with bit blv. the saa7165 is controllable via the i 2 c-bus. formatting y and uv the input data formats are formatted into the internally used processing formats (separate for 4 :2:2 and 4:1:1 formats). the iff, ifc and ifl bits control the input data format and determine the right interpolation filter (see figs 10 to 13). peaking and coring peaking is applied to the y signal to compensate several bandwidth reductions of the external pre-processing. y signals can be improved to obtain a better sharpness. there are the two switchable bandpass filters bf1 and bf2 controlled via the i 2 c-bus by the bits bp1, bp0 and bfb. thus, a frequency response is achieved in combination with the peaking factor k (figs 5 to 9; k is determined by the bits bfb, wg1 and wg0). the coring stage with controllable threshold (4 states controlled by co1 and co0 bits) reduces noise disturbances (generated by the bandpass gain) by suppressing the amplitude of small high-frequent signal components. the remaining high-frequent peaking component is available for a weighted addition after coring. table 1 llc and mc con?guration modes in dmsd applications (note 1) note 1. yuv data are only latched with the rising edge of lcc at mc = high. pin input signal description llc llc (ll27) the data rate on yuv-bus is half the clock rate on pin llc, e.g. in saa7151b, saa7191 and saa7191b single scan operation. mc cref llc llc (ll27) the data rate on yuv-bus must be identical to the clock rate on pin llc, e.g. in double scan applications. mc mc = high llc llc (ll27) the data rate on yuv-bus must be identical to the clock rate on pin llc, e.g. saa9051 single scan operation. mc mc = high
1996 aug 20 7 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 table 2 data format 4 :2:2 table 3 data format 4 :1:1 input pixel byte sequence ( 4:2:2 format) y0 (lsb) y0 y0 y0 y0 y0 y0 y1 y1 y1 y1 y1 y1 y1 y2 y2 y2 y2 y2 y2 y2 y3 y3 y3 y3 y3 y3 y3 y4 y4 y4 y4 y4 y4 y4 y5 y5 y5 y5 y5 y5 y5 y6 y6 y6 y6 y6 y6 y6 y7 (msb) y7 y7 y7 y7 y7 y7 uv0 (lsb) u0 v0 u0 v0 u0 v0 uv1 u1 v1 u1 v1 u1 v1 uv2 u2 v2 u2 v2 u2 v2 uv3 u3 v3 u3 v3 u3 v3 uv4 u4 v4 u4 v4 u4 v4 uv5 u5 v5 u5 v5 u5 v5 uv6 u6 v6 u6 v6 u6 v6 uv7 (msb) u7 v7 u7 v7 u7 v7 y frame 012345 uv frame 0 2 4 input pixel byte sequence ( 4:1:1 format) y0 y0 y0 y0 y0 y0 y0 y0 y0 y1 y1 y1 y1 y1 y1 y1 y1 y1 y2 y2 y2 y2 y2 y2 y2 y2 y2 y3 y3 y3 y3 y3 y3 y3 y3 y3 y4 y4 y4 y4 y4 y4 y4 y4 y4 y5 y5 y5 y5 y5 y5 y5 y5 y5 y6 y6 y6 y6 y6 y6 y6 y6 y6 y7 y7 y7 y7 y7 y7 y7 y7 y7 uv0 00000000 uv1 00000000 uv2 00000000 uv3 00000000 uv4 v6 v4 v2 v0 v6 v4 v2 v0 uv5 v7 v5 v3 v1 v7 v5 v3 v1 uv6 u6 u4 u2 u0 u6 u4 u2 u0 uv7 u7 u5 u3 u1 u7 u5 u3 u1 y frame 01234567 uv frame 0 4
1996 aug 20 8 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.3 line control by href for 4:2:2 format, cref = 13.5 mhz; href = 720 pixel; 50 and 60 hz field. handbook, full pagewidth ll27 (llc) cref internal bus clock (llc2) href start of active line 0 u0 1 v0 2 u2 3 v2 4 u4 5 v4 6 u6 7 v6 y signal u and v signal 50 hz 60 hz byte number for pixels: y signal u and v signal meh268 0 u0 1 v0 2 u2 3 v2 4 u4 5 v4 6 u6 7 v6 handbook, full pagewidth ll27 (llc) cref internal bus clock (llc2) href y signal u and v signal end of active line 714 v714 715 u716 716 v716 717 u718 718 v718 719 u714 50 hz meh269 714 v714 715 u716 716 v716 717 u718 718 v718 719 u714 60 hz byte number for pixels: y signal u and v signal a. start of active line. b. end of active line.
1996 aug 20 9 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 interpolation the chrominance interpolation filter consists of various filter stages, multiplexers and de-multiplexers to increase the data rate of the colour-difference signals by a factor of 2 or 4. the switching of the filters by the bits iff, ifc and ifl is described previously. additional signal samples with significant amplitudes between two consecutive signal samples of the low data rate are generated. the time-multiplexed u and v samples are stored in parallel for converting. data switch the digital signals are adapted to the conversation range. u and v data have 8-bit formats again; y can have 9 bits dependent on peaking. blanking and switching to colourless level is applied here. bits can be inverted by inv-bit to change the polarity of colour-difference output signals. digital colour transient improvement (dcti) the dcti circuit improves the transition behaviour of the uv colour-difference signals. as the cvbs signal allows for a 4:1:1 bandwidth representation only, the dcti improves the transients to the same performance as signals coming from a 4 :2:2 source, or even more. in order to obtain the point of inflection, the second derivative of the signal is calculated. the improved transition is centred with respect to the point of inflection of the original signal. thus, there is no horizontal shift of the resulting signal. the transition area length to be improved is controlled via i 2 c-bus by the bits li1 and li0 (table 5); the sensitivity of the dcti block is controlled by the bits ga1 and ga0. the cmo bit controls the colour detail sensitivity. it should be set to logic 1 (on) if the video signal contains fine colour details (recommended operation mode). digital-to-analog converters (dacs) conversion is separate for y, u and v. the converters use resistor chains with low-impedance output buffers. the minimum output voltage is 200 mv to reduce integral non-linearity errors. the analog signal, without load on output pin, is between 0.2 and 2.2 v floating. an application for 1 v/75 w on outputs is shown in fig.14. each digital-to-analog converter has its own supply and ground pins suitable for decoupling. the reference voltage, supplying the resistor chain of all three dacs, is the supply voltage v dda4 . the current into pin 41 is 0.3 ma; a larger current improves the bandwidth but increases the integral non-linearity. i 2 c-bus format table 4 i 2 c-bus format; see notes 1 to 7 notes 1. s = start condition. 2. slave address = 1011 111x. 3. a = acknowledge; generated by the slave. 4. subaddress = subaddress byte (table 5); if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. 5. data = data byte (table 5). 6. p = stop condition. 7. x = r/ w control bit: a) x = 0; order to write (the circuit is slave receiver). b) x = 1; order to read (the circuit is slave transmitter). s slave address a subaddress a data 0 a ... data n a p
1996 aug 20 10 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 table 5 i 2 c-bus transmission table 6 bit functions in data bytes table 7 logic levels and function of co1 and co0 table 8 logic levels and function of afb, bp1, bp0 and bfb subaddress function data bits d7 d6 d5 d4 d3 d2 d1 d0 01 peaking and coring afb co1 co0 bp1 bp0 bfb wg1 wg0 02 input formats; interpolation iff ifc ifl cmo li1 li0 ga1 ga0 03 input/output setting 0 0 dc1 dc0 drp blv r78 inv bit description co1 and co0 control of coring threshold; see table 7 afb, bp1, bp0, bfb bandpass ?lter selection; see table 8 bfb, wg1 and wg0 peaking factor k; see table 9 iff, ifc and ifl input format and ?lter control at 13.5 mhz data rate; see table 10 cmo choice modi?cation; 0 = modi?cation off; 1 = modi?cation on. li1 and li0 dcti timing range; see table 11 ga1 and ga0 dcti gain factor; see table 12 dc1 and dc0 delay compensation of luminance signal; see table 13 drp uv input data code; 0 = twos complement; 1 = offset binary blv blanking level on y output; 0 = 16 lsb; 1 = 0 lsb r78 yuv input data solution; 0 = 7-bit data; 1 = 8-bit data inv polarity of colour-difference output signals: 0 = normal polarity equal to input signal 1 = inverted polarity data bits function co1 co0 0 0 coring off 0 1 small noise reduction 1 0 medium noise reduction 1 1 high noise reduction data bits function afb bp1 bp0 bfb x 0 0 0 characteristic (see fig.5) x 0 1 0 characteristic (see fig.6) x 1 0 0 characteristic (see fig.7) x 1 1 0 characteristic (see fig.8) 0 x x 1 bf1 filter bypassed (see fig.9a) 1 x x 1 bf1 filter bypassed (see fig.9b)
1996 aug 20 11 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 table 9 logic levels and function of bfb, wg1 and wg0 table 10 logic levels and function of iff, ifc and ifl data bits function bfb wg1 wg0 000k= 1 8 ; minimum peaking 001k= 1 4 010k= 1 2 0 1 1 k = 1; maximum peaking 1 0 0 k = 0; peaking off 101k= 1 4 ; minimum peaking 110k= 1 2 1 1 1 k = 1; maximum peaking data bits function iff ifc ifl 0 0 0 4:1:1 format; - 3 db attenuation at 1.6 mhz video frequency; (see fig.10) 0 0 1 4:1:1 format; - 3 db attenuation at 600 khz video frequency; (see fig.11) 0 1 x 4:1:1 format; - 3 db attenuation at 1.2 mhz video frequency; (see fig.12) 1 0 0 4:2:2 format; - 3 db attenuation at 1.6 mhz video frequency; (see fig.10) 1 0 1 4:2:2 format; - 3 db attenuation at 600 khz video frequency; (see fig.11) 1 1 x 4:2:2 format; - 3 db attenuation at 2.5 mhz video frequency; (see fig.13) table 11 logic levels and function of li1 and li0 table 12 logic levels and function of ga1 and ga0 data bits range li1 li0 0 0 +4 to - 4 0 1 +6 to - 6 1 0 +8 to - 8 1 1 +12 to - 12 data bits factor ga1 ga0 0 0 off 01 1 4 10 1 2 111 table 13 logic levels and function of dc1 and dc0 data bits delayed clock cycles dc1 dc0 000 01+1 10 - 2 11 - 1
1996 aug 20 12 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 limiting values in accordance with the absolute maximum rating system (iec134). note 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. thermal characteristics symbol parameter min. max. unit v ddd1 digital supply voltage 1 (pin 12) - 0.3 +7 v v ddd2 digital supply voltage 2 (pin 31) - 0.3 +7 v v dda1 analog supply voltage 1 (pin 32) - 0.3 +7 v v dda2 analog supply voltage 2 (pin 37) - 0.3 +7 v v dda3 analog supply voltage 3 (pin 40) - 0.3 +7 v v dda4 analog supply voltage 4 (pin 42) - 0.3 +7 v v ddd digital supply voltage - 0.5 +7 v d v gnd difference voltage v ssd - v ssa - 100 mv v i voltage on all input pins 4 to 11, 14 to 27 and 41 - 0.3 v ddd v v o voltage on analog output pins 33, 36 and 39 - 0.3 v ddd v v esd electrostatic handling for all pins 2000 - v p tot total power dissipation 0 tbf mw t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 70 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 46 k/w
1996 aug 20 13 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 characteristics v ddd = 4.5 to 5.5 v; v dda = 4.75 to 5.25 v; llc = ll27; mc = cref = 13.5 mhz; t amb = 0 to 70 c; measurements taken in fig.14; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd1 supply voltage range (pin 12) for digital part 4.5 5 5.5 v v ddd2 supply voltage range (pin 31) for digital part 4.5 5 5.5 v v dda1 supply voltage range (pin 32) for buffer of dac 1 4.75 5 5.25 v v dda2 supply voltage range (pin 37) for buffer of dac 2 4.75 5 5.25 v v dda3 supply voltage range (pin 40) for buffer of dac 3 4.75 5 5.25 v v dda4 supply voltage range (pin 42) dac reference voltage 4.75 5 5.25 v i ddd supply current (i ddd1 +i ddd2 ) for digital part - tbf tbf ma i dda supply current (i dda1 +i dda4 ) for dacs and buffers - tbf tbf ma yuv-bus inputs (pins 4 to 11 and 14 to 21) (see figs 3 and 4) v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2.0 - v ddd + 0.5 v c i input capacitance v i = high -- 10 pf i li input leakage current -- 4.5 m a inputs ap, sp, mc, llc, href and reset (pins 22 to 27) v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2.0 - v ddd + 0.5 v c i input capacitance v i = high -- 10 pf i li input leakage current -- 4.5 m a v 24 mc input voltage for ll27 27 mhz data rate 2.0 - v ddd + 0.5 v cref signal on mc input cref data rate; note 1 --- v i 2 c-bus scl and sda (pins 28 and 29) v il low-level input voltage - 0.5 - +1.5 v v ih high-level input voltage 3.0 - v ddd + 0.5 v i i input current v i = low or high -- 10 m a v ack output voltage at acknowledge (pin 29) i 29 =3ma -- 0.4 v i 29 output current during acknowledge 3 -- ma digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44) v dac input reference voltage for internal resistor chains (pin 42) 4.75 5 5.25 v i cur input current (pin 41) r 41-42 =15k w- 300 -m a v 1,44 reference voltage low pin connected to v ssa1 - 0 - v c l external blocking capacitor to v ssa1 for reference voltage high (pins 2 and 43) - 0.1 -m f f llc data conversation rate (clock) fig.3 -- 36 mhz
1996 aug 20 14 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 notes 1. yuv-bus data is read at mc = high (pin 24) clocked with llc (see fig.5); data is read only with every second rising edge of llc when cref = 1 2 llc on pin 24. 2. 0.2 to 2.2 v output voltage range at 8-bit dac input data; the data word can increase to 9-bit dependent on peaking factor. 3. the luminance signal is set to the digital black level: 16 lsb for blv-bit = 0; 0 lsb for blv-bit = 1. 4. the chrominance amplitudes are set to the digital colourless level of 128 lsb. 5. the circuit is prepared for a new data initialization. res dac resolution luminance dac - 9 - bits chrominance dacs - 8 - bits ile dc integral linearity error 8-bit data -- 1.0 lsb dle dc differential error 8-bit data -- 0.5 lsb y, (r - y) and (b - y) analog outputs (pins 33, 36 and 39) v o(p-p) output signal voltage (peak to peak value) without load - 2 - v v 33,36,39 output voltage range without load; note 2 0.2 - 2.2 v v 39 output blanking level y output; note 3 - 16 - lsb v 33,36 output no-colour level (r - y), (b - y); note 4 - 128 - lsb r 33,36,39 internal serial output resistance - 25 -w r l33,36,39 output load resistance external load 125 -- w b output signal bandwidth - 3db 20 -- mhz t d signal delay from input to y output - tbf - ns lcc timing (pin 25) (see fig.3) t llc cycle time 27.7 37 41 ns t ph pulse width 40 50 60 % t r rise time -- 5ns t f fall time -- 6ns yuv-bus timing (pins 4 to 11 and 14 to 21) (see fig.5) t su;dat input data set-up time 10 -- ns t hd;dat input data hold time 3 -- ns mc timing (pin 24) (see fig.5) t su;dat input data set-up time 10 -- ns t hd;dat input data hold time 3 -- ns reset timing (pin 27) t su set-up time after power-on or failure active low; note 5 4 t llc -- ns
1996 aug 20 15 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.4 yuv-bus data and cref timing. handbook, full pagewidth meh270 1.5 v input clock llc (ll27) input data yuv-bus, cref (mc) 0.6 v 2.0 v t su;dat(min) t hd;dat(min) t hd;dat t llc data valid t f t r t llch 0.8 v 2.4 v table 14 yuv-bus data processing delay processing delay llc cycles remarks yuv digital input 66 at mc = 1 yuv analog output 132 at mc = 1 2 llc
1996 aug 20 16 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.5 peaking frequency response with i 2 c-bus control bits bp1 = 0; bp0 = 0 and bfb = 0. handbook, full pagewidth meh271 03 2 45 12 16 10 14 8 6 4 2 0 f y (mhz) v y (db) 1 6 7 (1) (2) (3) (4) (1) k = 1 (2) k = 1 2 (3) k = 1 4 (4) k = 1 8 fig.6 peaking frequency response with i 2 c-bus control bits bp1 = 0; bp0 = 1 and bfb = 0. handbook, full pagewidth meh272 03 2 45 12 16 10 14 8 6 4 2 0 f y (mhz) v y (db) 1 6 7 (1) (2) (3) (4) (1) k = 1 (2) k = 1 2 (3) k = 1 4 (4) k = 1 8
1996 aug 20 17 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.7 peaking frequency response with i 2 c-bus control bits bp1 = 1; bp0 = 0 and bfb = 0. handbook, full pagewidth meh273 03 2 45 12 16 10 14 8 6 4 2 0 f y (mhz) v y (db) 1 6 7 (1) (2) (3) (4) (1) k = 1 (2) k = 1 2 (3) k = 1 4 (4) k = 1 8 fig.8 peaking frequency response with i 2 c-bus control bits bp1 = 1; bp0 = 1 and bfb = 0. handbook, full pagewidth meh274 03 2 45 12 16 10 14 8 6 4 2 0 f y (mhz) v y (db) 1 6 7 (1) (2) (3) (4) (1) k = 1 (2) k = 1 2 (3) k = 1 4 (4) k = 1 8
1996 aug 20 18 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.9 peaking frequency response with i 2 c-bus control bits bp1 = 0; bp0 = 0 and bfb = 1; bandpass filter bf1 bypassed and peaking off. handbook, full pagewidth meh470 03 2 45 2 6 0 4 f y (mhz) v y (db) 1 6 7 8 10 - 2 - 4 (1) (2) (3) (4) handbook, full pagewidth meh471 03 2 45 2 6 0 4 f y (mhz) v y (db) 1 6 7 8 10 - 2 - 4 (1) (2) (3) (4) a. afb = 0. b. afb = 1. (1) k = 1 (2) k = 1 2 (3) k = 1 4 (4) k = 0
1996 aug 20 19 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.10 interpolation filter at dcti off with i 2 c-bus control bits iff = 0; ifc = 0 and ifl = 0 in 4 : 1 : 1 format and control bits iff = 1; ifc = 0 and ifl = 0 in 4 : 2 : 2 format; 13.5 mhz data rate. handbook, full pagewidth meh474 03 2 45 - 24 - 20 - 16 - 12 - 8 - 4 0 f y (mhz) v u (db) 1 6 7 - 28 - 32 fig.11 interpolation filter at dcti off with i 2 c-bus control bits iff = 0; ifc = 0 and ifl = 1 in 4 : 1 : 1 format and control bits iff = 1; ifc = 0 and ifl = 1 in 4 : 2 : 2 format; 13.5 mhz data rate. handbook, full pagewidth meh473 03 2 45 - 24 - 20 - 16 - 12 - 8 - 4 0 f y (mhz) v u (db) 1 6 7 - 28 - 32
1996 aug 20 20 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 fig.12 interpolation filter at dcti off with i 2 c-bus control bits iff = 0; ifc = 1 and ifl = 0 in 4:1:1 format; 13.5 mhz data rate. handbook, full pagewidth meh472 03 2 45 - 24 - 20 - 16 - 12 - 8 - 4 0 f y (mhz) v u (db) 1 6 7 - 28 - 32 fig.13 interpolation filter with i 2 c-bus control bits iff = 1; ifc = 1 and ifl = x in 4 : 2 : 2 format; 13.5 mhz data rate. handbook, full pagewidth meh475 03 2 45 - 48 - 40 - 32 - 3 db - 24 - 16 - 8 0 f y (mhz) v u (db) 1 6 7 - 56 - 64
1996 aug 20 21 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 application information handbook, full pagewidth mbh537 interpolation filter y formatter 0.1 m f dcti saa7165 y u v data switch dac 3 41 42 cur v dda4 25 w 36 peaking and coring dac 2 dac 1 uv formatter timing control i 2 c-bus control test control 40 v dda3 37 v dda2 32 v dda1 31 + 5 v v ddd2 12 13 v ssd1 v ddd1 data clock 21 to 14 8 y7 to y0 11 to 4 24 27 25 26 28 29 8 uv7 to uv0 cref ll27 mc llc href reset scl sda yuv-bus i 2 c-bus 25 w 33 (b - y) 25 w 50 w 1 v (p - p) 75 w 39 1 15 k w y c uv refl uv refl y 2 c y 43 44 30 v ssd2 22 ap 23 sp 34 v ssa1 35 v ssa2 38 v ssa3 3 sub 0.1 m f 0.1 m f + 5 v + 5 v 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f (1) (1) 50 w 1 v (p - p) 75 w (1) (1) (r - y) 50 w 1 v (p - p) 75 w (1) (1) fig.14 application diagram. (1) output amplitude determined by resistors (r l > 125 w ).
1996 aug 20 22 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 package outline unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b references outline version european projection issue date iec jedec eiaj mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot187-2 d (1) 16.66 16.51 h d 17.65 17.40 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e e e d 16.00 14.99 0.630 0.590 16.00 14.99 0.630 0.590 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 92-11-17 95-02-25 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
1996 aug 20 23 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all plcc packages. the choice of heating method may be influenced by larger plcc packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 aug 20 24 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 aug 20 25 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 notes
1996 aug 20 26 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 notes
1996 aug 20 27 philips semiconductors product speci?cation video enhancement and digital-to-analog processor (veda2) saa7165 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca51 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 825 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 615 800, fax. +358 615 80920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros, tel. +30 1 4894 339/911, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 657021/1200/02/pp28 date of release: 1996 aug 20 document order number: 9397 750 01047

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